1. Field of the Invention
The present application relates generally to integrated circuits, and in particular, to a computer implemented method, data processing system, and computer program product for measuring impedance of microprocessor chips, circuit boards, and electronic packaging using a pseudo-impulse response.
2. Description of the Related Art
Improvements in manufacturing processes are enabling integrated circuit devices to offer more functionality as the size of individual transistors contained therein get smaller and smaller, thus allowing more transistors to be packaged within an integrated circuit device. Integrated circuits (also called chips) are coupled to a substrate utilizing an integrated circuit package. The package is responsible for supplying power to the integrated circuit, and physically supplying the circuit's signals out of the chip to the circuit board.
As the trend of integrating more functions in a single high performance integrated circuit device continues, the on-chip noise condition due to switching activity on the chip has become a challenge. High frequency noise can hinder desired increases in clock cycle time as well as reliability improvements for these highly integrated systems on a chip. To optimally mitigate noise due to switching activity on the chip, impedance in the chip/package/board power supply system may be measured to assist in determining the origins of the noise and optimizing the design of the system. Impedance is a crucial parameter for determining the workloads or switching charge activity that a microprocessor can tolerate without causing any logic problems. However, measuring the impedance can be difficult since the impedance in modern microprocessor chips is small, the impedance in the frequency range of interest is broad (e.g., ˜kHz to 1 GHz), and there is no one localized point to measure the current of the chip/package/board to obtain the impedance.
There currently are methods in the art for measuring the impedance in power supply systems. Examples of such methods are described in U.S. Pat. No. 6,768,952 B2 to Kantorovich et al. and in U.S. Pat. No. 6,911,827 B2 also to Kantorovich et al. The '952 and '827 patents both disclose measuring impedance by determining the transition between current levels to generate a periodic current waveform, and taking multiple measurements of the voltage of the system in the time domain to obtain a plurality of sets of voltage measurements. The methods remove clock frequency-dependent noises to generate a filtered average voltage (since the clock speed is known, the position in the time domain where the clock signal will repeat is also known, thereby allowing for the determination of where the voltage peak occurs and consequently the removal of the to form a filtered average voltage). The methods then determine the impedance by dividing a Fourier component of the filtered average voltage by a Fourier component of a periodic current waveform.
However, the impedance-measuring techniques in the Kantorovich patents contains several drawbacks, such as requiring one to perform manual filtering processes to remove noise, as well as requiring that multiple measurements be taken of the current at various frequencies. For instance, the Kantorovich techniques measure the transition between two very active states, resulting in a lot of noise that needs to be filtered out. The Kantorovich patents disclose “removing the clock frequency-dependent noises to generate a filtered average voltage”. However, the manual filtering proposed by the Kantorovich patents may potentially change the frequency spectrum. In other words, if an element is removed from the time domain, it may not be possible to known the impact the removal will have on the frequency domain.
Therefore, it would be advantageous to have an improved method for measuring impedance of microprocessor chips, circuit boards, and electronic packaging.